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Senior Staff Place & Route Engineer

Irvine, CA 92612

Posted: 08/01/2019 Employment Type: Direct Placement Category: Engineers-All Other Job Number: 82906
  • Responsible for timing closure, physical verification and power integrity signoff for block level and chip
  • Analytical & problem-solving skills to debug clock tree and timing
  • Ability to debug and solve DRC and LVS problems
  • Ability to analyze and solve static and dynamic voltage drop, electro migration for chip.
  • Place and route flow, timing and SI closure, synthesis, timing analysis, power and IR drop analysis, formal verification, MMMC, flat and hierarchical flow, ECO, physical design methodology, prototyping etc.
  • Must be a team player with an eye on innovation and automation to reduce turnaround time for chips
  • Solid communication skills to interact with ASIC and analog design teams

 

Required Skills
  • Knowledge and experience with floorplan, placement, Clock tree synthesis and routing is a must
  • Should be familiar with parasitic extraction, signal integrity and static timing analysis
  • Place and route tool: Innovus/ICC2 experience for floorplan, place, clock tree [CTS], routing, SI and timing closure
  • Static Timing Analysis tools such as Tempus/Primetime
  • Static and dynamic IR tools such as Redhawk/Voltus
  • Physical verification tools such as Calibre for DRC & LVS
  • Knowledge of scripting using Tcl, Perl and unix shell script
  • BS/MS with 5 to 7 years of experience
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